32 processing groups × 8 values · 16 rounds · one core · 23 execution slots per cycle.
Each cell is one emitted instruction slot, not one SIMD element. Slot lanes indicate bundle order, not persistent execution threads.
Wheel to zoom around the pointer; drag to pan. Click a cell to inspect; use operation buttons to follow dependencies. Yellow = selected operation (all pieces) · Cyan = direct predecessors · Pink = direct successors.
Dark cells are genuinely empty slots; muted colored cells are filtered instructions. Utilization always counts the full, unfiltered schedule (and the current cycle window). Empty capacity is not necessarily fillable: readiness, engine compatibility, whole-operation completion, memory ordering, and scratch lifetimes constrain placement. Connections show only the selected operation’s direct IR dependencies, including explicit memory edges. The IR can conservatively include operands of alternative engine spellings; it is not a complete physical-register hazard graph.